A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics

A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs

Reukers, Matthijs (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Quantum & Computer Engineering)

Hofstee, H.P. (mentor)
Al-Ars, Z. (graduation committee)
Peltenburg, J.W. (graduation committee)
van Leuken, T.G.R.M. (graduation committee)

Delft University of Technology

Computer Engineering

2022-07-08

Tydi is an open specification for streaming dataflow designs in digital circuits, allowing designers to express how composite and variable-length data structures are transferred over streams using clear, data-centric types. This provides a higher-level method for defining interfaces between components as opposed to existing bit- and byte-based interface specifications.

In this thesis, an open-source intermediate representation (IR) is introduced which allows for the declaration of Tydi's types. The IR enables creating and connecting components with Tydi Streams as interfaces, called Streamlets. It also lets backends for synthesis and simulation retain high-level information, such as documentation. Types and Streamlets can be easily reused between multiple projects, and Tydi’s streams and type hierarchy can be used to define interface contracts, which aid collaboration when designing a larger system.

The IR codifies the rules and properties established in the Tydi specification and serves to complement computation-oriented hardware design tools with a data-centric view on interfaces. To support different backends and targets, the IR is focused on expressing interfaces, and complements behavior described by hardware description languages and other IRs. Additionally, a testing syntax for the verification of inputs and outputs against abstract streams of data, and for substituting interdependent components, is presented which allows for the specification of behavior.

To demonstrate this IR, a grammar, parser, and query system have been created, and paired with a backend targeting VHDL.

Hardware description languages and compilation
Design reuse and communication-based design
Transaction-level verification
Intermediate representations
Open-source software
Hardware streams

http://resolver.tudelft.nl/uuid:f2cf3430-328c-4489-9f79-ce1d739eae47

2022-11-03

Student theses

master thesis

© 2022 Matthijs Reukers