Tile-Based rasterization on an embedded Tile-based MPSoC

Tile-Based rasterization on an embedded Tile-based MPSoC

Splinter, J.

Cotofana, S.D. (mentor)
Molnos, A.M. (mentor)

Electrical Engineering, Mathematics and Computer Science

Computer Engineering

Computer Engineering

2011-10-19

Graphics on a computer are often handled by a graphics pipeline. Rasterization is an important stage in this pipeline. It converts the basic elements of computer graphics, triangles, into the basic elements of a screen, pixels. This stage is very computation intensive and has a large memory footprint. The last decade a lot of research has been dedicated to tile-based rasterization. This technique divides an image into smaller images called tiles. These can be stored on a smaller memory, hence reducing the memory footprint of the rasterization process. Several software and hardware implementations of tile-based rasterization exist. They use a single general purpose processor, or make use of multiple specialized cores, such as Graphical Processing Units (GPUs). Although GPUs prove to be very fast in graphical applications, their effectiveness in running other applications is limited. This is a potential drawback in embedded systems where the available resources are very limited. In Embedded Systems typically Multiple Processors are used in a System on Chip, an MPSoC. This work will make a parallelization study to investigate the performance of rasterization on a MPSoC. To perform this study we modify a tile-based rasterizer to make efficient use of multiple embedded processors. This modified rasterizer is used to evaluate the impact of various configurations on the execution time of the rasterizer. For example the size of an image tile, the size of the communication buffer and the number of processors will be varied in our experiments. Increasing the size of an image tile proves to decrease the execution time only to a certain point, after which the execution time will start to increase. Furthermore, using a larger communication buffer increases the load balancing and decreases the execution time. It is concluded that with the right load balancing adding processors to the system will decrease the time needed to rasterize an image.

rasterization
MPSoC
embedded
tile-based
microblaze
FPGA
CoMPSoC

http://resolver.tudelft.nl/uuid:f43422a6-ef31-4f61-ae7a-f71d3b3c645b

Student theses

master thesis

(c) 2011 Splinter, J.