Zero-settling errors by exploiting common zeros in the Wafer Stage/Reticle Stage feedforward design

Zero-settling errors by exploiting common zeros in the Wafer Stage/Reticle Stage feedforward design

Ochoa Navarrete, M.

Heertjes, M.F. (mentor)
Munnig Schmidt, R.H. (mentor)

Mechanical, Maritime and Materials Engineering

Precision and Microsystems Engineering

2014-10-30

In synchronization of high-precision stages systems, particularly the one between the wafer stage system and the reticle stage system of a wafer scanner, a novel feedforward control structure capable of achieving zero-settling errors is presented. The synchronization is achieved by including finite impulse response (FIR) filters both in the input and feedforward paths of the control loop. In an iterative process, the coefficients of three FIR filters (a wafer stage feedforward filter, a reticle stage feedforward filter, and an identical wafer stage/reticle stage input shaping filter) are obtained by minimizing a cost function involving the error of each individual stage system and the net error, the latter being the performance indicator. Tracking performance will be demonstrated by simulations and experimental results obtained from an industrial wafer scanner.

feedforward
input shaping
FIR filtering
self-tuning
synchronization
settling error

http://resolver.tudelft.nl/uuid:00eaecc5-dbcd-41eb-8dd8-52fbbdeff172

Student theses

master thesis

(c) 2014 Ochoa Navarrete, M.