Reconfigurable Trigger Logic for Electronic Instrumentation in Space Applications

Reconfigurable Trigger Logic for Electronic Instrumentation in Space Applications

Lefter, M.

Cotofana, S.D. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

2010-07-06

Future space missions have to rely on advanced, smart and very light payloads in order to explore the solar system within a reasonable cost envelope. For this reason, efforts are made to obtain higher levels of integration that can reduce costs and allow the presence of more and more instruments on board of small spacecrafts. With the advent of radiation hardened FPGAs, the use of reprogrammable hardware in space is no longer an issue. This opens new perspectives to space electronics. System-on-Chip (SoC) design methodologies for future highly-integrated devices are actively promoted by space agencies. In this thesis we focus on FPGA based SoC architectures for space electronics instrumentation, targeting time related issues. In this line of reasoning we proposed and developed a highly customizable trigger logic block able to reject background events with the highest possible efficiency and to accurately time-stamp the accepted ones. Its features include programmable coincidence window, input ordering, and for every input in particular the possibility to choose different states and to program the delay. The trigger logic block is designed as an AMBA IP core and it can be interfaced with many SoC libraries. For testing purposes we have programmed an AMBA based SoC architecture including a LEON3 on-chip processor and a minimal selection of IP cores from the GRLIB library on a Xilinx XC3S1500 FPGA. The trigger logic IP together with another IP developed for testing reasons were clocked at 100 MHz, while the rest of the system was running at 40 MHz. An average dead time of 1.5 µs was obtained, corresponding to an events frequency of 0.65 MHz. Based on our experimental results we can conclude that the proposed trigger logic approach can potentially successfully function in space applications. In extent to the trigger logic IP design, we have further performed research on the current SpaceWire time-codes, in an attempt to improve the inter-module time distribution accuracy. Several methods were proposed to reach synchronization in the order of nanoseconds, as opposed to the current microseconds synchronization, with little changes over the current SpaceWire standard.

Trigger
SpaceWire
SoC
AMBA
LEON3
FPGA

http://resolver.tudelft.nl/uuid:14195160-aaca-4fad-a44f-5bbba35b36f3

2010-07-07

Student theses

master thesis

(c) 2010 Lefter, M.