Throughput and Power optimization of the Range Trie design for IP lookups

Throughput and Power optimization of the Range Trie design for IP lookups

Mastrogiannopoulos, D.P.

Sourdis, I. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Computer Engineering

2012-10-19

This thesis aims to improve the Range Trie design on throughput and power consumption. The Range Trie is an SRAM based design that offers competitive performance and is scalable enough to withstand current and future expectations, especially the transition from IPv4 to IPv6. This thesis is exploring the possibilities in partitioning the last and larger in size levels of the Range Trie while replicating the first ones which require less area. For the purposes of this thesis a goal of up to four times the initial throughput was set, on the Range Trie for address lookups. Various partitioning configurations were examined to determine the most advantageous one for performance and feasibility. Apart from throughput, partitioning proved to be beneficial also for power. Synopsys tools were used to synthesize the design along with a UMC 90nm process. Power figures were extracted for a variety of configurations for both IPv4 and IPv6 protocols, up to 16M prefixes large. These figures were compared with previous ones made for the original design to detect any improvement. Results have shown that power was almost halved at most cases while throughput increased by nearly 400%.

internet
range trie
ip lookup

http://resolver.tudelft.nl/uuid:1c2f845a-1afe-4488-9446-97e9b4252b60

Student theses

master thesis

(c) 2012 Mastrogiannopoulos, D.P.