Bit-error rate measurement setup and comparator design

Title

Bit-error rate measurement setup and comparator design

 Author

Agah, A.

Contributor

Bult, K. (mentor)
Long, J. (mentor)

Faculty

Electrical Engineering, Mathematics and Computer Science

 Department

microelectronics

 Date

2009-07-01

 Abstract

Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design of high speed ADCs. BER measurement setup is introduced and implemented in this thesis. Using this BER measurement setup gives us the opportunity to compare the BER of different comparators. It also enables us to study the effect of different parameters such as bias current, and power supply variations on the BER of these comparators. Capacitive based comparator is also proposed in this work which is a new topology for comparators and simulations show that it can perform better than the other conventional comparators with respect to BER. The capacitive based comparator and 2 conventional comparators are implemented in the BER measurement setup so that they can also be compared on silicon.

 Subject

Comparator
Bit error rate
BER
ADC
measurement
low power
high speed
capacitive

 To reference this document use:

http://resolver.tudelft.nl/uuid:388babf0-9db0-40df-be95-5c1ecc072254

 Embargo date

2011-05-01

 Part of collection

Student theses

 Document type

master thesis

 Rights

(c) 2009 Agah, A.
Files
PDF AmirAgah-thesis.pdf 2.32 MB
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