Print Email Facebook Twitter High Performance Histograms on SIMT and SIMD Architectures Title High Performance Histograms on SIMT and SIMD Architectures Author Berger, M.E.R. Contributor Varbanescu, A. (mentor) Faculty Electrical Engineering, Mathematics and Computer Science Department Software and Computer Technology Programme Parallel and Distributed Systems Group Date 2015-12-16 Abstract Using the histogram procedure, this work studies performance determining factors in computing in parallel on SIMD and SIMT devices. Modern graphics pro-cessing units (GPUs) support SIMT, multiple threads running the same instruction, whereas central processing units (CPUs) use SIMD, in which one instruction op-erates on multiple operands. As part of this work, a cross-technology framework is developed that allows testing a single-source histogram implementation on multiple devices, providing insight into the performance of various API – hardwareconfigurations. It is shown that in the presence of high contention, the implementation of atomic operations becomes of great influence on performance. This work provides guidelines for the choice between devices based on image features and hardware specifications. Subject GPUCUDAOpenCLhistogramatomics To reference this document use: http://resolver.tudelft.nl/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7 Coordinates 51.9987265, 4.3732723 Part of collection Student theses Document type master thesis Rights (c) 2015 Berger, M.E.R. Files PDF thesis.pdf 2.7 MB Close viewer /islandora/object/uuid:38dd2dbd-9dca-4a27-8829-06ea069af6b7/datastream/OBJ/view