Print Email Facebook Twitter Performance Estimation of a Processor Module in the Real-Time Motion Control Platform of an ASML Lithostepper Title Performance Estimation of a Processor Module in the Real-Time Motion Control Platform of an ASML Lithostepper Author Voskes, Jurriaan (TU Delft Electrical Engineering, Mathematics and Computer Science; TU Delft Computer Engineering) Contributor Cotofana, Sorin (mentor) van Leuken, Rene (graduation committee) van de Ven, J (graduation committee) Degree granting institution Delft University of Technology Date 2018-05-16 Abstract At the core of state of the art microelectronic industry's drive for better technology, lies the continuing advancement in the development of Integrated Circuits using highly complex lithography machines, known as lithosteppers, which embed complex mechanical sub-systems performing intricate motions. These systems are controlled by means of custom real-time computing platforms containing off-the-shelf and specialized hardware components, and are optimized to keep pace with the continuing growing trend in performance requirements. At the ASML Twinscan lithostepper's heart resides the Control Architecture Reference Model (CARM) motion control platform which manages, among others, the wafer-stage, a multiple degree of freedom module, able to position a 15 kg heavy wafer-table with nanometer accuracy at extremely high acceleration and velocity. As the industry requirements for feature-size, overlay accuracy, and throughput keep increasing, the ASML lithosteppers, and the CARM platform in particular, should anticipate these demands by making early changes and upgrades with respect to computational performance and accuracy. Given that the current lithostepper configurations are not capable of sustaining the anticipated updates, which requires the increase of the control loop execution frequency from 20kHz to 40kHz, an early evaluation of potential CARM High Performance Process Controller (HPPC) successors has been performed. This indicated that the NXP-Freescale T4240 processor can potentially fulfill the expected requirements, however, the evaluation lacks accuracy as it was performed on a benchmark code not reflecting the actual CARM workload. To circumvent this problem, in this thesis, we introduce a more accurate evaluation methodology, which relies on the actual motion control application running on the HPPC and is able to capture aspects as scheduling, parallelism, and processor resource usage. To this end we develop a set of custom performance benchmarks able to emulate the CARM environment and evaluate the Freescale T4240 processor in this new context. Our results indicate that the T4240 is able to deliver enough computation power to fulfill the control loop execution frequency upscaling requirement from 20kHz to 40kHz. Additionally, we demonstrate that due to its clustered hardware architecture one T4240 can sustain 20kHz loop execution frequency for the workload of three current HPPCs, which suggest that its utilization in current lithosteppers can be beneficial. Subject Performance EstimationBenchmarkProcessorMulticorePowerPC To reference this document use: http://resolver.tudelft.nl/uuid:442661d0-9f6b-4930-94a4-6d40af7ae2c6 Embargo date 2019-05-16 Part of collection Student theses Document type master thesis Rights © 2018 Jurriaan Voskes Files PDF Thesis_JVoskes_2018_Perfo ... module.pdf 4.94 MB Close viewer /islandora/object/uuid:442661d0-9f6b-4930-94a4-6d40af7ae2c6/datastream/OBJ/view