Title
A design of ultra-low phase noise CMOS oscillator based on series-resonance
Author
GU, Lunan (TU Delft Electrical Engineering, Mathematics and Computer Science)
Contributor
Babaie, M. (mentor) 
Sebastiano, F. (graduation committee)
Alavi, S.M. (graduation committee)
Kiavar, A. (graduation committee)
Degree granting institution
Delft University of Technology
Programme
Electrical Engineering
Date
2023-11-03
Abstract
The current trend in the state-of-the-art oscillators achieves low phase noise performance. Such stringent performance is demanded in modern Communication Systems. This thesis proposes the design of a CMOS oscillator achieving the ultra-low phase noise. This design is based on TSMC 40 nm technology, the supply voltage is 1.1 V, and the oscillation frequency is fstart=6.65 GHz and fstop=7.58 GHz, the tuning range is calculated to be 13 % with the Phase Noise@ 1 MHz(normalized to 10 GHz) varies from -128.1 dBc/Hz to -130.4 dBc/Hz and Figure of Merit varies from 188.0 dBc/Hz to 190.0 dBc/Hz, consuming average power of 95 mW and the fcorner is 250 kHz. Since the chip is still in fabrication and the final result only includes the simulation result. Further work involves the measurement and performance validation.
Subject
CMOS
oscillator
phase noise
voltage-controlled oscillator
To reference this document use:
http://resolver.tudelft.nl/uuid:73c3d4ee-a4a4-4903-8044-3d2dfa9bd81f
Embargo date
2025-11-03
Part of collection
Student theses
Document type
master thesis
Rights
© 2023 Lunan GU