Scheduling in Partially Buffered Crossbar Switches

Scheduling in Partially Buffered Crossbar Switches

Cao, D.

Mhamdi, L. (mentor)

Electrical Engineering, Mathematics and Computer Science

Microelectronics & Computer Engineering

Embedded Systems

2011-06-30

Intensive studies have been conducted to identify the most suitable architecture for high-performance packet switches. These architectures can be classified by queuing schemes, scheduling algorithms and switching fabric structures. The crossbar based switching fabric has been widely agreed to be the most suitable one, for its low cost, scalability and native multicast support. Large numbers of commercial implementations and literature studies have been conducted on the unbuffered crossbar switching architecture. Due to the requirement of the centralized scheduler, scheduling algorithms in the unbuffered crossbar have generally high complexities. This leads to time-consuming scheduling processes that prevent the unbuffered architecture from scaling up with the modern optical link operating at the Gb/S range. The buffered crossbar architecture has been proposed to overcome the scheduling complexity bottleneck faced by the unbuffered crossbar. The introduction of cross point buffers decouples the centralized scheduling process and lowers the scheduling complexity. However, the drawback of the buffered crossbar lies in the fact that it requires $N^2$ expensive on-chip memories, $N$ being the size of the switch, limiting the scalability of the buffered crossbar architecture. To provide the scheduling simplicity brought by the buffered crossbar while having a cost close to the unbuffered one, the partially buffered crossbar architecture has been proposed. With the combination of advantages of the previous two architectures, the Partially Buffered Crossbar (PBC) is deemed as one of the competitive candidates for next-generation switching architectures. However, the previously proposed algorithms did not fully exploit its potential. In this thesis, we: i) propose a unicast scheduling algorithm that further pushes the performance of the PBC switch under various non-uniform traffic settings, while using as few as 2 internal buffers per output. ii) study the multicast traffic support by the partially buffered crossbar switch and come up with an effective multicast scheduling algorithm.

Partially Buffered Crossbar

http://resolver.tudelft.nl/uuid:853277e1-19ad-4a18-8b60-f57b98dded38

Student theses

master thesis

(c) 2011 Cao, D.