Void Formation in Cu/Sn Interconnections in Flip Chip Package

Void Formation in Cu/Sn Interconnections in Flip Chip Package

Chen, Wei-En (TU Delft Mechanical, Maritime and Materials Engineering)

Popovich, V. (mentor)
Mavinkurve, Amar (graduation committee)
Hermans, M.J.M. (graduation committee)

Delft University of Technology

Materials Science and Engineering

2020-09-30

The sporadic occurrence of voids within intermetallic compounds during microelectronic soldering is a key factor affecting the reliability of electronic solder joints. This study aims to understand the void formation mechanisms and investigate different soldering effects. Cu/Sn solder joints in flip chip packages were examined at 190°C after zero to four weeks thermal aging. Experimental approach included ion milling and plasma focused ion beam (PFIB) cross sectional examination, while simulation approach such as finite element modeling (FEM) was used to support the results. Results showed voids presence at Cu6Sn5/solder interface after three weeks aging due to the large local tensile stress induced by volume shrinkage associated with intermetallic compounds formation. These voids have tendency to self-heal after four weeks aging by a compressive stress that originates from the solder ball shrinkage. Compressive stress of 59 MPa was found sufficient to close the 3 µm void. Moreover, higher level of carbon and organic additives during the electroplating of Cu substrates showed a remarkable effect on the impurities incorporation, which in turn has led to more Krikendall voids at Cu3Sn/Cu interfaces. This suggests that by avoiding C and O impurities on Cu substrates, there will be less voids and thus more reliable joints. Furthermore, solder joints in Cu/Sn/Cu sandwich structure without underfill were found to release volume shrinkage stress by height reduction and thus resulting in no voids formation. On the contrary, in structures that have underfill filled in between the solder joints, stress will accumulate to a higher level when the volume intends to shrink and stimulates voids to form. The simulated strain in solder joints with the underfill can be as high as 60 % while it can only be 25 % without the underfill. Both experimental results and FEM suggest that voids have higher forming tendency when subjected to the underfill. Last but not the least, cracks will generate due to large mismatch of coefficient of thermal expansion (CTE) when solder joints undergo multiple reflows. Underfill can compensate the large difference and suppress the cracks formation. Consequently, the application of underfill is very crucial for voids formation and solder joints reliability. 

flip chip
Cu-Sn
Voids

http://resolver.tudelft.nl/uuid:cb259b1e-2d01-45cd-b59b-83bd2ba87424

Student theses

master thesis

© 2020 Wei-En Chen