Design techniques for a stable operation of cryogenic field-programmable gate arrays

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Homulle, Harald (TU Delft OLD QCD/Charbon Lab; TU Delft QuTech Advanced Research Centre)
Visser, Stefan (Student TU Delft)
Patra, B (TU Delft OLD QCD/Charbon Lab; TU Delft QuTech Advanced Research Centre)
Charbon-Iwasaki-Charbon, E. (TU Delft OLD QCD/Charbon Lab; TU Delft (OLD)Applied Quantum Architectures; TU Delft QuTech Advanced Research Centre)

2018-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

http://resolver.tudelft.nl/uuid:d7130747-ec56-406a-851c-13154f8f32d1

https://doi.org/10.1063/1.5004484

0034-6748

Review of Scientific Instruments, 89 (1)

Institutional Repository

journal article

© 2018 Harald Homulle, Stefan Visser, B Patra, E. Charbon-Iwasaki-Charbon