An Ultrasound Receiver ASIC Employing Compressive Sensing

An Ultrasound Receiver ASIC Employing Compressive Sensing

Mirzaei, Farzad (TU Delft Electrical Engineering, Mathematics and Computer Science)

Pertijs, M.A.P. (mentor)

Delft University of Technology

Electrical Engineering | Microelectronics

2018-09-27

This work introduces an architecture that is capable of reducing the number of cables coming out of an ultrasound receiver ASIC by a substantial factor without dropping the frame-rate. It employs a newly developed technique named compressive sensing to exploit the ultrasound signal redundancies in the spatial domain.
There are 32 receive paths of which the signal is amplified, multiplied by a random weight, summed in groups of 8 elements and digitized using 4 charge-sharing SAR ADCs. A 100MHz clock is used on the chip to time-multiplex the outputs of the 4 ADCs on a 10-bit parallel output. The ASIC mainly consists of three parts: (1) a low noise amplifier and trans-conductor, (2) a summation node and ADC, (3) and the digital programming circuitry and control signals.
The AFE consumes 1.1 mW power per channel and 1.5 mW power per channel including the SAR ADC power consumption. The received signal has a center frequency of 5MHz with a 50% bandwidth and it is being sampled at a rate of 25MHz.
A prototype chip has been fabricated in TSMC 0.18μm LV technology. Post-layout simulation results of this chip are presented in this thesis. The design is element-matched to a linear array of 32 PZT elements with 150μm pitch. The chip is rectangular shaped with dimensions of 5mm ✕ 1mm.

Compressive sensing
Cable count reduction
Current summation
Random-weighting Trans-conductance amplifier

http://resolver.tudelft.nl/uuid:d7233d41-0a60-4293-ba8f-e7189fdc4c69

Student theses

master thesis

© 2018 Farzad Mirzaei