Title
CMOS Drivers for RF-DACs
Author
El Boustani, Ossama (TU Delft Electrical Engineering, Mathematics and Computer Science)
Contributor
de Vreede, L.C.N. (mentor)
Bootsman, R.J. (mentor) 
Alavi, S.M. (graduation committee)
Sebastiano, F. (graduation committee)
Gajadharsing, John (graduation committee)
Degree granting institution
Delft University of Technology
Programme
Electrical Engineering
Project
Digital Transmitter ICs (DRASTIC)
Date
2023-06-05
Abstract
This work describes a fully digital transmitter (DTX) for 5G mMIMO base stations that combines the strengths of high-speed digital CMOS with the high-power capabilities of a Monolithic Microwave Integrated Circuit (MMIC) high-voltage technology. This technology platform offers high integration and scalability for implementing Radio Frequency Digital-to-Analog Converters (RF-DACs). To facilitate the digital operation of the gate-segmented output power stage, a custom VT-shifted LDMOS technology has been utilized. The relatively high output capacitance of the LDMOS devices makes digital class-C operation the preferred class of operation to achieve high efficiency with good linearity metrics for the digital power amplifier (DPA). In this work, we analyze this operation, assuming a trapezoidal-shaped current profile, which allows investigation of the impact of the non-zero rise and fall times on the theoretical (normalized) output power and drain efficiency.
To drive the gate segments in this custom VT LDMOS technology with a gate-to-source voltage (VGS) swing of 2.2 V, a driver is proposed comprising: inverter chains, a level shifter, and a high-voltage output buffer. This driver is fully digital and can be implemented using thin-oxide bulk CMOS devices whose VDD is limited to 1.1 V. A model of the DTX comprising only the drivers and DPA at the circuit level is created in ADS to evaluate the output power, drain efficiency, and system efficiency. The DTX is simulated at 3.5 GHz full power and achieves an output power of 19.79 W/23.43 W, a drain efficiency of 67.28%/59.22%, and a system efficiency of 60.34%/54.48% with a non-empirical and empirical model of LDMOS, respectively. Rise and fall times of around 20% of the RF cycle (tr = tf = 0.2/fc) are found to be the most suitable in terms of power consumption and system efficiency.
Subject
RF-DAC
Polar DTX
CMOS Driver
Custom VT LDMOS
Digital Class-C
To reference this document use:
http://resolver.tudelft.nl/uuid:e7ae220e-3554-4435-8ce6-ec9679f57e45
Embargo date
2025-06-01
Part of collection
Student theses
Document type
master thesis
Rights
© 2023 Ossama El Boustani