Efficient Methodology for ISO26262 Functional Safety Verification

Efficient Methodology for ISO26262 Functional Safety Verification

Augusto da Silva, F. (TU Delft Computer Engineering; Cadence Design Systems)
Bagbaba, Ahmet Cagri (Cadence Design Systems)
Hamdioui, S. (TU Delft Quantum & Computer Engineering)
Sauer, Christian (Cadence Design Systems)

Gizopoulos, Dimitris (editor)
Alexandrescu, Dan (editor)
Papavramidou, Panagiota (editor)
Maniatakos, Michail (editor)

Quantum & Computer Engineering

2019-07-01

Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.

ATPG
Fault Injection Simulation
Formal Methods
Functional Safety
ISO26262

http://resolver.tudelft.nl/uuid:edcf4101-c914-4fe9-9ec4-6935bc00e21d

https://doi.org/10.1109/IOLTS.2019.8854449

IEEE, Piscataway

978-1-7281-2491-9

2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019

25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, 2019-07-01 → 2019-07-03, Rhodes, Greece

2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019

Accepted author manuscript

Institutional Repository

conference paper

© 2019 F. Augusto da Silva, Ahmet Cagri Bagbaba, S. Hamdioui, Christian Sauer