Print Email Facebook Twitter Efficient Memory Architecture for Next Generation Low-Power Embedded Systems Title Efficient Memory Architecture for Next Generation Low-Power Embedded Systems Author Mohapatra, Sourav (TU Delft Electrical Engineering, Mathematics and Computer Science) Contributor Kortbeek, V. (mentor) Pawełczak, Przemysław (graduation committee) Degree granting institution Delft University of Technology Programme Electrical Engineering | Embedded Systems Date 2022-08-26 Abstract In this thesis we propose a novel memory architecture design that is robust to frequent memory failures targeting next generation low power embedded system. We explore the how the architecture works and perform detailed evaluations to show that our system achieves better performance than the state-of-the-art. Subject Embedded SystemsLow powermemory To reference this document use: http://resolver.tudelft.nl/uuid:fbee1b8a-4670-4464-ae44-1cf29617c4ab Embargo date 2024-08-01 Part of collection Student theses Document type master thesis Rights © 2022 Sourav Mohapatra Files file embargo until 2024-08-01